Product Manager

Normal is an applied AI company solving the hardest problems in AI and silicon. It builds foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. The team works as one across New York City, Silicon Valley (Mountain View), and London. The early-career Product Manager will help build the AI systems and autoresearch platform the ASIC team needs to tapeout unconventional, physics-based architecture, with domains of exploration including RTL optimization, design verification, and continual learning from experiment results.

Responsibilities

Help decide what to build for the ASIC team's AI systems and autoresearch platform; Work with the Product Lead and engineering teams to deliver incremental milestones to tapeout; Investigate where the ASIC team's time goes and be accountable for whether tooling gets used; Write requirements docs, specs, and user journeys that engineering builds from; Build prototypes where they communicate faster than documents; Work with engineers to turn promising prototypes into production-ready tools; Work in the codebase with coding agents, open PRs for bug fixes or UI changes, and learn from code reviews

Requirements

A degree in CS, EE, physics, math, or similar, or the equivalent taught to yourself; 1-3 years of experience in product management, engineering, research, technical program management, or a related technical role; You can point to something that was your idea and that you made real; Fluency with coding agents (e.g., Claude Code, Codex, Cursor, or similar) as a normal part of how you work; Experience building or evaluating LLM-powered products; Clarity of communication in both speaking and writing; Comfort with ambiguity and the ability to frame a vague problem and come back with a proposal; Interest in how chips are designed

Nice to have

Coursework, research, or internship experience in chip architectures, digital design, verification, or hardware performance modeling; Exposure to SystemVerilog; Familiarity with the mechanisms underlying LLM inference